 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 SST34HF16818 Mb Flash (x16) Concurrent SuperFlash ComboMemory Advance Specifications FEATURES: * Flash Organization: 1M x16 * Dual-Bank Architecture for Concurrent Read/Write Operation - 16 Mbit: 12 Mbit + 4 Mbit * SRAM Organization: - 8 Mbit: 512K x16 * Single 2.7-3.3V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 25 mA (typical) - Standby Current: 20 A (typical) * Hardware Sector Protection (WP#) - Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading data array * Sector-Erase Capability - Uniform 1 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Read Access Time - Flash: 70 and 90 ns - SRAM: 70 and 90 ns * Latched Address and Data * Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Word-Program Time: 14 s (typical) - Chip Rewrite Time: 8 seconds (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * JEDEC Standard Command Set * Conforms to Common Flash Memory Interface (CFI) * Packages Available - 56-ball LFBGA (8mm x 10mm) PRODUCT DESCRIPTION The SST34HF1681 ComboMemory devices integrate a 1M x16 CMOS flash memory bank with a 512K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST's proprietary, highperformance CMOS SuperFlash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF1681 devices are ideal for applications such as cellular phones, GPSs, PDAs and other portable electronic devices in a low power and small form factor system. The SST34HF1681 features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 4 Mbit and 12 Mbit with top or bottom sector protection options for storing boot code, program code, configuration/parameter data and user data. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 1 The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF1681 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high performance Word-Program, the flash memory banks provide a typical Word-Program time of 14 sec. The entire flash memory bank can be erased and programmed word-by-word in typically 8 seconds for the SST34HF1681, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF1681 devices contain onchip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SST, the SST logo, and SuperFlash are Trademarks registered by Silicon Storage Technology, Inc. in the U.S. Patent and Trademark Office. Concurrent SuperFlash, CSF, and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications SRAM bank enable signal, BES1# and BES2, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF1681 are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. CONCURRENT READ/WRITE STATE TABLE Flash Bank 1 Read Write Write No Operation Write No Operation Bank 2 Write Read No Operation Write No Operation Write SRAM No Operation No Operation Read Read Write Write Note: For the purposes of this table, write means to Block-, Sector, or Chip-Erase, or Word-Program as applicable to the appropriate bank. Device Operation The SST34HF1681 uses BES1#, BES2 and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. Flash Read Operation The Read operation of the SST34HF1681 is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). Flash Word-Program Operation The SST34HF1681 are programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 10 s. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Concurrent Read/Write Operation Dual bank architecture of SST34HF1681 devices allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Figure 1 for Dual-Bank Memory Organization. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 2 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Flash Sector/Block-Erase Operation The Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. The SST34HF1681 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Ready/Busy# (RY/BY#) The SST34HF1681 includes a Ready/Busy# (RY/BY#) output signal. During any SDP initiated operation, e.g., Erase, Program, CFI or ID Read operation, RY/BY# is actively pulled low, indicating a SDP controlled operation is in Progress. The status of RY/BY# is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Bank-Erase, the RY/BY# is valid after the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull up resistor. Ready/ Busy# is in high impedance whenever OE# or CE# is high or RST# is low. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after RY/BY# goes high. Flash Chip-Erase Operation The SST34HF1681 provide a Chip-Erase operation, which allows the user to erase all unprotected sectors/blocks to the "1" state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Flash Data# Polling (DQ7) When the SST34HF1681 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling (DQ7) is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block- or ChipErase, the Data# Polling (DQ7) is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 22 for a flowchart. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ7 becomes true data. Flash Write Operation Status Detection The SST34HF1681 provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/ Busy# (RY/BY#) pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, (c)2001 Silicon Storage Technology, Inc. Flash Toggle Bits (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operS71214-00-000 12/01 561 3 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications ation. The Toggle Bit (DQ6) is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 22 for a flowchart. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ6 no longer toggles. Software Data Protection (SDP) The SST34HF1681 provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF1681 are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 are "Don't Care" during any SDP command sequence. Data Protection The SST34HF1681 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Common Flash Memory Interface (CFI) The SST34HF1681 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Hardware Block Protection The SST34HF1681 provide a hardware block protection which protects the outermost 4 KWord in Bank 1. The block is protected when WP# is held low. See Figure 1 for BlockProtection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. Product Identification The Product Identification mode identifies the device as the SST34HF1681 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 23 for the ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION ADDRESS Manufacturer's ID Device ID SST34HF1681 0001H 2761H T1.0 561 Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 18). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 17). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 17 and 18 for timing diagrams. DATA 00BFH 0000H (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 4 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 16 for timing waveform and Figure 23 for a flowchart. and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM Read and Write data byte control modes of operation. SRAM Read The SRAM Read operation of the SST34HF1681 is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. SRAM Write SRAM Operation With BES1# low, BES2 and BEF# high, the SST34HF1681 operates as 512K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST34HF1681 SRAM is mapped into the first 512 KWord address space. When BES1#, BEF# are high and BES2 is low, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# The SRAM Write operation of the SST34HF1681 is controlled by WE# and BES1#, both have to be low, BES2 have to be high for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagram, Figures 4 and 5, for further details. FUNCTIONAL BLOCK DIAGRAM AMS - A0 Address Buffers SuperFlash Memory (Bank 1) RST# BEF# WP# LBS# UBS# WE# OE# BES1# BES2 RY/BY# SuperFlash Memory (Bank 2) Control Logic I/O Buffers DQ15 - DQ0 Address Buffers AMS = Most significant address 8 Mbit SRAM 561 ILL B1.2 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 5 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block 31 Block 30 Block 29 Bank 2 Bank 1 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 4 KWord Sector Protection (Four 1 KWord Sectors) Block 0 561 ILL F02.0 FIGURE 1: SST34HF1681, 1 MBIT X 16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 6 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TOP VIEW (balls facing down) 8 7 6 5 4 3 2 A7 A11 A8 A15 A12 A19 NC A13 A9 NC A14 A10 A16 NC NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 DQ4 VDDS NC DQ3 VDDF DQ11 WE# BES2 NC WP# RST# RY/BY# LBS# UBS# A18 A6 A3 A5 A2 A17 A4 A1 DQ1 DQ9 DQ10 DQ2 VSS OE# A0 DQ0 DQ8 1 BEF# BES1# ABCDEFGH SST34HF1681 561 ILL F03.0 FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM TABLE 2: PIN DESCRIPTION Symbol 1 X 10MM) COMBOMEMORY PINOUT Pin Name Functions To provide flash address, A19-A0. To provide SRAM address, A18-A0 To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. To activate the Flash memory bank when BEF# is low AMS to A0 Address Inputs DQ15-DQ0 Data Inputs/Outputs BEF# BES1# BES2 OE# WE# UBS# LBS# WP# RST# RY/BY# Flash Memory Bank Enable SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Write Protect Reset Ready/Busy# To gate the data output buffers To control the Write operations To enable DQ15-DQ8 To enable DQ7-DQ0 To protect and unprotect sectors from Erase or Program operation To Reset and return the device to Read mode To output the status of a Program or Erase Operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. 2.7-3.3V Power Supply to Flash only 2.7-3.3V Power Supply to SRAM only Unconnected pins T2.1 561 VSS Ground Power Supply (Flash) Power Supply (SRAM) No Connection VDDF VDDS NC 1. AMS = Most Significant Address (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 7 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 3: OPERATIONAL MODES SELECTION1 Mode Full Standby Output Disable BEF# VIH VIH VIL Flash Read Flash Write Flash Erase SRAM Read VIL VIL VIL VIH BES1# VIH X VIL VIL VIH X VIH X VIH X VIH X VIL BES22 X VIL VIH VIH X VIL X VIL X VIL X VIL VIH VIL VIH VIL VIH VIL SRAM Write VIH VIL VIH X VIL VIL VIH VIL Product Identification3 1. 2. 3. 4. OE# X X VIH X VIH VIL VIH VIH WE# X X VIH X VIH VIH VIL VIL LBS# X X X VIH X X X X UBS# X X X VIH X X X X VIL VIL VIH VIL VIL VIH X DQ0-7 HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT HIGH-Z DOUT DIN HIGH-Z DIN DQ8-15 HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT DOUT HIGH-Z DIN DIN HIGH-Z VIL VIH X X VIL VIL VIH X Manufacturer's ID4 Device ID4 T3.2 561 X can be VIL or VIH, but no other value. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time Software mode only With A19-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0=0, SST34HF1681 Device ID = 2761H, is read with A0=1 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 8 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software ID Entry5 CFI Query Entry5 Software ID Exit/ CFI Exit6 1. 2. 3. 4. 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 AAH AAH AAH AAH AAH AAH AAH 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 80H 90H 98H F0H 4th Bus Write Cycle Addr1 WA3 5555H 5555H 5555H Data2 Data AAH AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 6th Bus Write Cycle Addr1 SAX4 BAX4 5555H Data2 30H 50H 10H T4.1 561 Address format A14-A0 (Hex),Address A19-A15 can be VIL or VIH, but no other value, for the Command sequence. Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence. WA = Program Word address SAX for Sector-Erase; uses A19-A11 address lines BAX, for Block-Erase; uses A19-A15 address lines 5. The device does not remain in Software Product Identification Mode if powered down. 6. With A20-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0=0 SST34HF1681 Device ID = 2761H, is read with A0=1. TABLE 5: CFI QUERY IDENTIFICATION STRING1 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H T5.0 561 Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) 1. Refer to CFI publication 100 for more details. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 9 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 6: SYSTEM INTERFACE INFORMATION Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP Min (00H = no VPP pin) VPP Max (00H = no VPP pin) Typical time out for Word-Program 2N s (24 = 16 s) Typical time out for Min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Word-Program 2N times typical (21 x 24 = 32 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T6.0 561 TABLE 7: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 001FH 0000H 0000H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T7.0 561 Data Device size = 2N Byte (15H = 21; 221 = 2M Bytes) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FF = 1023) z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001F = 31) (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 10 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. VDD = VDDF and VDDS 2. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C OF VDD 2.7-3.3V 2.7-3.3V AC CONDITIONS TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 19 and 20 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 11 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 8: DC OPERATING CHARACTERISTICS (VDD = VDDF Limits Symbol IDD Parameter Active VDD Current Read Flash SRAM Concurrent Operation Write1 Flash SRAM ISB IRT ILI ILO VIL VILC VIH VIHC VOLF VOHF VOLS VOHS Standby VDD Current Reset VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Low Voltage Flash Output High Voltage SRAM Output Low Voltage SRAM Output High Voltage 2.2 0.7 VDD VDD-0.3 0.2 3.0V 3.3V 40 30 40 75 30 1 1 0.8 0.3 mA mA A A A A A V V V V V V 0.4 V V 35 30 60 mA mA mA Min Max Units Test Conditions Address input = VIL/VIH, at f=1/TRC Min, VDD=VDD Max, all DQs open OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH, or BES2=VIL BEF#=VIH, BES1#=VIL , BES2=VIH BEF#=VIH, BES1#=VIL , BES2=VIH WE#=VIL BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH BEF#=VIH, BES1#=VIL , BES2=VIH VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC Reset=VSS0.3V VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min IOL =1 mA, VDD=VDD Min IOH =-500 A, VDD=VDD Min T8.1 561 AND VDDS = 2.7-3.3V) VDD-0.2 1. IDD active while Erase or Program is in progress. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 12 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ1 TPU-WRITE 1 Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s T9.0 561 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: CAPACITANCE Parameter CI/O 1 (Ta = 25C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 20 pF 16 pF T10.1 561 CIN1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: FLASH RELIABILITY CHARACTERISTICS Symbol NEND TDR1 ILTH1 1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T11.0 561 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 13 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications AC CHARACTERISTICS TABLE 12: SRAM READ CYCLE TIMING PARAMETERS SST34HF1681-70 Symbol TRCS TAAS TBES TOES TBYES TBLZS 1 SST34HF1681-90 Min 90 Max 90 90 45 90 0 0 0 Units ns ns ns ns ns ns ns ns 35 35 45 10 ns ns ns ns T12.0 561 Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# to Active Output Output Enable to Active Output UBS#, LBS# to Active Output BES# to High-Z Output Output Disable to High-Z Output UBS#, LBS# to High-Z Output Output Hold from Address Change Min 70 Max 70 70 35 70 0 0 0 25 25 35 10 TOLZS1 TBYLZS1 TBHZS1 TOHZS TOHS 1 TBYHZS1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: SRAM WRITE CYCLE TIMING PARAMETERS SST34HF1681-70 Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# to End-of-Write Output Disable from WE# Low Output Enable from WE# High Data Set-up Time Data Hold from Write Time 0 30 0 Min 70 60 60 0 60 0 60 30 0 40 0 Max SST34HF1681-90 Min 90 80 80 0 80 0 80 40 Max Units ns ns ns ns ns ns ns ns ns ns ns T13.0 561 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 14 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TABLE 14: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V SST34HF1681-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Low to Active Output OE# Low to Active Output BEF# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Pin Low to Read 0 500 50 100 0 0 20 20 0 500 50 100 Min 70 70 70 35 0 0 30 30 Max SST34HF1681-90 Min 90 90 90 45 Max Units ns ns ns ns ns ns ns ns ns ns ns s T14.0 561 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase. TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA1 TBY1 TBR1 TSE TBE TSCE Parameter Word-Program Time Address Setup Time Address Hold Time WE# and BEF# Setup Time WE# and BEF# Hold Time OE# High Setup Time OE# High Hold Time BEF# Pulse Width WE# Pulse Width WE# Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time RY/BY# Delay Time Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase 90 1 25 25 100 0 40 0 0 0 10 40 40 30 30 30 0 150 Min Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ms T15.2 561 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 15 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TOHS BES2 TBES TBLZS TBHZS TOES TOLZS TOHZS TBYES TBYLZS TBYHZS DATA VALID 561 ILL F04.0 OE# UBS#, LBS# DQ15-0 AMSS = Most Significant SRAM Address FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS WE# TAWS TBWS BES1# BES2 TBWS TBYWS UBS#, LBS# TODWS TOEWS TDSS TDHS NOTE 2 DQ15-8, DQ7-0 NOTE 2 VALID DATA IN 561 ILL F05.0 Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance. If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 16 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TWCS ADDRESSES AMSS-0 TWPS WE# TWRS TBWS BES1# BES2 TBWS TAWS TASTS TBYWS UBS#, LBS# TDSS DQ15-8, DQ7-0 TDHS NOTE 2 VALID DATA IN NOTE 2 561 ILL F06.0 Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 17 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TRC ADDRESS A19-0 TCE BEF# TOE OE# VIH WE# TCLZ TOH DATA VALID TOLZ TAA TOHZ TCHZ HIGH-Z DATA VALID 561 ILL F07.0 DQ15-0 HIGH-Z FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM TBP ADDRESS A19-0 5555 TAH TWP WE# TAS OE# TCH BEF# TCS RY/BY# TDS DQ15-0 TDH XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. VALID 561 ILL F08.2 2AAA 5555 ADDR TWPH TBY TBR FIGURE 7: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 18 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TBP ADDRESS A19-0 5555 TAH TCP BEF# TAS OE# TCH TCPH 2AAA 5555 ADDR WE# TCS RY/BY# DQ15-0 TBY TDS TDH TBR XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID 561 ILL F09.2 Note: X can be VIL or VIH, but no other value. FIGURE 8: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM ADDRESS A19-0 TCE BEF# TOEH OE# TOE WE# TBR DQ7 DATA# DATA# VALID DATA 561 ILL F10.1 TOES FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 19 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications ADDRESS A19-0 TCE BEF# TOEH OE# TOE WE# TBR DQ6 TWO READ CYCLES WITH SAME OUTPUTS VALID DATA 561 ILL F11.2 FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555 TSCE BEF# OE# TWP WE# TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 TBR VALID 561 ILL F12.2 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 15) X can be VIL or VIH, but no other value. FIGURE 11: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 20 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA BAX TBE BEF# OE# TWP WE# TBY RY/BY# TBR DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 561 ILL F13.2 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 15) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 12: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA SAX TSE BEF# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 561 ILL F14.2 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 15) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 13: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 21 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001 BEF# OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX90 TAA 00BF Device ID 561 ILL F15.2 TIDA Device ID = 2761H for SST34HF1681 Note: X can be VIL or VIH, but no other value FIGURE 14: FLASH SOFTWARE ID ENTRY AND READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555 BEF# OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX98 561 ILL F16.1 TIDA TAA Note: X can be VIL or VIH, but no other value. FIGURE 15: FLASH CFI ENTRY AND READ (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 22 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 5555 2AAA 5555 DQ15-0 XXAA XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 561 ILL F17.1 Note: X can be VIL or VIH, but no other value FIGURE 16: FLASH SOFTWARE ID EXIT/CFI EXIT RY/BY# 0V RST# TRP BEF#/OE# TRHR 561 ILL F26.0 FIGURE 17: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS) (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 23 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications TRY RY/BY# RST# TRP BEF# OE# 561 ILL F19.1 TBR FIGURE 18: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION) VIHT INPUT VILT 561 ILL F20.0 VIT REFERENCE POINTS VOT OUTPUT AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 561 ILL F21.0 FIGURE 20: A TEST LOAD EXAMPLE (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 24 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 561 ILL F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 21: WORD-PROGRAM ALGORITHM (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 25 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Internal Timer Program/Erase Initiated Toggle Bit Program/Erase Initiated Data# Polling Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Program/Erase Completed Read same word No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 561 ILL F23.0 FIGURE 22: WAIT OPTIONS (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 26 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX98H Address: 5555H Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 561 ILL F24.1 Note: X can be VIL or VIH, but no other value. FIGURE 23: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 27 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications Chip-Erase Command Sequence Load data: XXAAH Address: 5555H Sector-Erase Command Sequence Load data: XXAAH Address: 5555H Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 561 ILL F25.0 Note: X can be VIL or VIH, but no other value. FIGURE 24: ERASE COMMAND SEQUENCE (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 28 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications PRODUCT ORDERING INFORMATION Device Speed Suffix1 XX Suffix2 XX Package Modifier P = 56 balls Package Type L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Bank Split 1 = 12M + 4M SRAM Density 0 = No SRAM 8 = 8 Mbit Flash Density 16 = 16 Mbit Voltage H = 2.7-3.3V Device Family SST34HF16xx - XXX Valid combinations for SST34HF1681 SST34HF1681-70-4C-L1P SST34HF1681-90-4C-L1P SST34HF1681-70-4E-L1P SST34HF1681-90-4E-L1P Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 29 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory SST34HF1681 Advance Specifications PACKAGING DIAGRAMS BOTTOM VIEW TOP VIEW 10.00 0.20 5.60 0.80 8 7 6 5 4 3 2 1 0.80 ABCDEFGH A1 CORNER 1.30 0.10 HGFEDCBA 5.60 8.00 0.20 8 7 6 5 4 3 2 1 0.45 0.05 (56X) A1 CORNER SIDE VIEW 56ba-LFBGA-L1P-8x10-450mic-ILL.1 0.15 SEATING PLANE 0.35 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. X 56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM SST PACKAGE CODE: L1P 10MM Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com (c)2001 Silicon Storage Technology, Inc. S71214-00-000 12/01 561 30 |
Price & Availability of SST34HF1601-70-4C-L1P
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |